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i ntegrated c ircuits d ivision ds-NCD2100-r02 www.ixysic.com 1 features ? wide capacitance range of 6.6pf to 37.553pf ? small step size: 0.063pf ? digitally select up to 1024 capacitance values. ? operating supply voltage range of 2.5v to 5.5v ? minimal current draw: i dd =1 ? a (typical) ? industrial temperature range -40 ? cto+85 ? c ? very small size dfn: 2 mm x 2 mm (0.079 in x 0.079 in) tsot: 2.9 mm x 2.8 mm (0.114 in x 0.110 in) ? moisture sensitivity level 1 applications ? vcxos ? crystal oscillators ? tunable rf stages ? filter tuning ? rfid tags ? industrial wireless controls ? capacitive sensor trimming description the NCD2100 is an eeprom based digitally programmable variable capacitor that provides capacitive offset trimming for capacitance sensitive circuits. programming the non-volatile eeprom register value or implementing on demand capacitance value changes are easily accomplished by means of the simple two-wire serial bus. providing 1024 discrete capacitance values over a nominal value range of 6.6pf to 37.553pf with step sizes of 0.063pf, the NCD2100 is well suited to ensure proper operation of capacitive critical circuits. additionally, to ensure interoperability over a broad array of design environments, the NCD2100 is rated for operation with supply voltages of 2.5v to 5.5v across the temperature range of -40 ? cto+85 ? c. ordering information figure 1. NCD2100 block diagram part # description NCD2100mtr NCD2100 dfn-6 in t&r (3000/reel) NCD2100ttr NCD2100 tsot-6 in t&r (3000/reel) da clk pv v dd x1 NCD2100 digital interface v ss cdac1 cdac2 cdac3 c 0 NCD2100 non-volatile digital programmable capacitor
i ntegrated c ircuits d ivision NCD2100 2 www.ixysic.com r02 1. specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 esd ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.6 general conditions for electrical characte ristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.7 capacitor electrical characteristics (pin x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.8 power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.9 digital interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.10 digital interface ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. performance data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 cdac1: capacitor segment 1 (10:9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 cdac2: capacitor segment 2 (8:6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 cdac3: capacitor segment 3 (5:1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5.1 shift register mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5.2 memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7 programming the non-volatile memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7.1 memory programming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7.2 programming control data into memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.8 verification of memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. load capacitance programming procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 capacitance trim code determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 programming the memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.1 all-bits programming mode (chk=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.2 single-bit programming mode (chk=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 programming verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 erasing the memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. manufacturing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 moisture sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 esd sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 soldering profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4 board wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5 mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5.1 NCD2100t tsot-6 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5.2 NCD2100ttr tsot-6 tape & reel specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5.3 NCD2100m dfn-6 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5.4 NCD2100mtr dfn-6 tape & reel specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
i ntegrated c ircuits d ivision NCD2100 r02 www.ixysic.com 3 1. specifications 1.1 package pinout 1.2 pin descriptions note: clk and da pins have a schmitt trigger input. x1 v ss pv v dd da clk 1 2 34 5 6 x1 1 v ss 2 v dd 3 pv 6 clk 5 da 4 pin name description tsot-6 package 1 x1 cdac output 2 v ss power supply ground 3 pv programming and verification i/o 4 clk serial bus clock input 5 da serial bus data input 6 v dd power supply voltage dfn-6 package 1 x1 cdac output 2 v ss power supply ground 3 v dd power supply voltage 4 da serial bus data input 5 clk serial bus clock input 6 pv programming and verification i/o
i ntegrated c ircuits d ivision NCD2100 4 www.ixysic.com r02 1.3 absolute maximum ratings absolute maximum electrical ratings are over the operating temperature range. absolute maximum ratings are stress ratings. stresses in excess of these ratings can cause permanent damage to the device. functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. 1.4 recommended operating conditions 1 v pv applied only when programming the eeprom. 1.5 esd ratings 1.6 general conditions for electrical characteristics typical values are characteristic of the device and are the result of engineering evaluations. they are provided for informational purposes only, and are not guaranteed by production testing. unless otherwise specified: specifications cover the operating temperature range t a =-40 ? c to +85 ? c, the supply voltage range v dd = 2.5v to 5.5v and v pv = 0v (or pin pv is open circuit). for testing purposes v dd = 5v, the logic low input voltage is 0v dc and the logic high input voltage is 5v dc . parameter minimum maximum unit supply voltage, v dd -v ss -0.3 + 6 v pins da, clk, and x1 voltage v ss -0.3 v dd + 0.3 v pin pv voltage v ss -0.3 7.5 v pv pulse width, t pv -80ms operating temperature, t a -40 +85 ? c storage temperature, t stg -55 +150 ? c parameter symbol minimum typical maximum unit supply voltage v dd 2.5 3.3 5.5 v x1 voltage v x1 --3 . 6v pv voltage 1 v pv 66 . 57 v pv pulse width t pv 40 50 80 ms operating temperature normal operation and shift register mode t a -40 - +85 c programming modes +20 - +30 parameter symbol conditions rating unit human body model hbm eia/jesd22-a114-d all pins except x1 + 2 kv pin x1 + 1 charged device model cdm eia/jesd22-c101-c all pins except x1 + 500 v pin x1 + 250
i ntegrated c ircuits d ivision NCD2100 r02 www.ixysic.com 5 1.7 capacitor electrical characteristics (pin x1) parameters measured at the nominal operating temperature of 255c, unless otherwise noted. notes: 1 contact the factory for operational capabilities beyond 250mhz. 2 simulation results (not measurements). 3 code=0 corresponds to ?00000000000? as seen in t he shift register (no additional capacitance). 4 code=1023 corresponds to ?11111111110? as seen in the shift re gister (maximum additional capacitance). chk = 0. 5 the chk bit is not used to determine the code?s decimal value. 6 capacitance variations due to temperature are always smaller t han 180ff between the nominal temperature (25c) and maximum or m inimum operating temperature. 1.8 power supply notes: 1 set v pv =0v or leave pin pv open circuit. 2 v pv =6.5v only when programming the eeprom. parameter test conditions symbol minimum typical maximum unit operational frequency range 1 - f x1 0.2 - 250 mhz variation of capacitance vs. v dd 2 code=0 3,5 , f=50mhz v dd =3.3v -2635 -2790 -2800 ppm/v v dd =5v dc/dv -4305 -4785 -4795 code=1023 4,5 , f=50mhz v dd =3.3v -390 -455 -505 v dd =5v -555 -705 -785 temperature drift 2 code=0 3,5 , f=50mhz v dd =3.3v -+207- ppm/c v dd =5v dc/dt - +204.4 - code=1023 4,5 , f=50mhz v dd =3.3v -+41.4- v dd =5v -+40.8- variation of capacitance vs. process 2 --- 2 5-+ 2 5% parameter symbol minimum typical maximum unit normal operation and shift register mode supply voltage v dd 2.5 3.3 5.5 v supply current i dd -15 0 ? a pv voltage 1 v pv -0-v power dissipation - - - 100 mw programming modes supply voltage v dd 4.75 5 5.25 v programming voltage 2 v pv 66 . 57 v programming current i pv --4m a programming verification supply voltage v dd 4.75 5 5.25 v
i ntegrated c ircuits d ivision NCD2100 6 www.ixysic.com r02 1.9 digital interface electrical characteristics 1.10 digital interface ac characteristics parameter conditions symbol minimum typical maximum unit input voltage logic 1 threshold clk and da v ih -- v dd -0.5 v logic 0 threshold clk, da and pv v il 0.5 - - hysteresis clk and da v ih - v il -0.2- output voltage pin pv with a 68k ? pull-up to v dd logic 1 v oh 0.6 v dd v logic 0 v ol 0.4 v dd pull-down resistors pins clk and da t a = +25 ? c r clk , r da 118 135 150 k ? t a = 25 5 ? c 116 154 -40 ? c < t a < +85 ? c 101 184 pin pv t a = +25 ? c r pv 157 180 203 k ? t a = 25 5 ? c 155 205 -40 ? c < t a < +85 ? c 135 245 input capacitance clk and da c clk , c da --1.2pf parameter conditions symbol minimum typical maximum unit serial clock frequency - f clk - - 120 khz duty cycle d clk 40 50 60 % serial data setup time - t setup 1--us hold time t hold 1--us shift register mode x1 valid delay clk = 1 t d_x1 --1us programming mode v dd = 5v, t a =25+ 5 ? c pv rising edge delay clk = 1 t d_pv 4--us pv pulse width v pv = 6.5v t pv 40 - 80 us clk falling edge delay pv = 0 t d_clk 0--us x1 valid delay clk = 0 t d_m-x1 --15us programming verification v dd = 5v, only one input bit = logic 0 pv output voltage valid delay clk = 1 t d_pv_out --4us power up delay: time before sending the first command after power supply reaches 95% of its value. - t sc 500 - - ? s
i ntegrated c ircuits d ivision NCD2100 r02 www.ixysic.com 7 figure 1: shift register mode timing diagram figure 2: programming mode timing diagram figure 3: programming verification timing diagram da clk lsb msb t setup t hold pv=0 t=0 t d_x1 x1 valid da clk lsb msb t setup t hold pv t=0 x1 valid t d_pv t pv t d_clk t d_m-x1 da * clk lsb msb t setup t hold t=0 t d_pv_out pv valid * only one data bit can be set to logic 0. pv indeterminate v oh v ol
i ntegrated c ircuits d ivision NCD2100 8 www.ixysic.com r02 2. performance data note: the performance data shown in the graphs above is typical of device performance. frequency (mhz) 0 100 200 300 400 500 capacitance (pf) 0 20 40 60 80 100 120 140 160 effective capacitance vs. frequency dfn packa g e code 1023 code 512 code 0 control code (decimal) 0 100 200 300 400 500 600 700 8 00 900 1000 1100 capacitance (pf) 0 5 10 15 20 25 30 35 40 capacitance vs. control code frequency (mhz) 0 100 200 300 400 500 capacitance (pf) 0 20 40 60 80 100 120 140 effective capacitance vs. frequency tsot packa g e code 1023 code 512 code 0 160
i ntegrated c ircuits d ivision NCD2100 r02 www.ixysic.com 9 note: the performance data shown in the graphs above is typical of device performance. capacitance (pf) 0 1020304050 quality factor 0 5 10 15 20 25 30 35 quality factor vs. capacitance tsot packa g e (f=200mhz) capacitance (pf) 0 5 10 15 20 25 30 35 40 45 quality factor 0 5 10 15 20 25 30 quality factor vs. capacitance dfn packa g e (f=200mhz) 35 400 500 0 10 20 30 40 50 60 70 80 90 100 frequency (mhz) 0 100 200 300 quality factor quality factor vs. frequency tsot packa g e code 512 code 1023 code 0 code 0 code 512 code 1023 frequency (mhz) 0 100 200 300 400 500 quality factor 0 10 20 30 40 50 60 70 80 90 100 quality factor vs. frequency dfn packa g e code 1023 code 0 code 512 code 0 code 512 code 1023 capacitance (pf) 0 10203040506070 80 quality factor 0 2 4 6 8 10 12 14 16 quality factor vs. capacitance dfn packa g e (f=400mhz)
i ntegrated c ircuits d ivision NCD2100 10 www.ixysic.com r02 3. functional description 3.1 introduction the NCD2100 provides a digita lly controlled variable capacitance between its x1 pin and v ss . the output capacitance is set by either the content of the shift register or by the content stored in the non-volatile memory. by default, the value of the capacitance at x1 is based on the digital value stored in memory, but can be controlled directly with the content of the input shift register, depending on the operating mode. the memory and shift register are 11 bits wide, and are organized as follows: the load capacitance presented by the NCD2100 at pin x1 is defined by: where: ? c 0 is the base load capacitance with a nominal value of 6.6pf, varying + 25% due to ic fabrication process variations. ? c 1 is the first coar se tuning capacitance. ? c 2 is the second coarse tuning capacitance. ? c 3 is the fine tuning capacitance. the NCD2100 has two operating modes: ? shift register mode (clk=1): the control data value loaded into the shift register determines the load capacitance. ? memory mode (clk=0): the control data value stored in the eeprom determines the load capacitance. in shift register mode the control data value must be shifted in after the device powers up and can be changed as needed. in memory mode, the default mode, the control data value is determined by the content of the internal memory that was programmed earlier. memory mode is applicable to situations in which the required output capacitance is unlikely to change and the control data must be retained across periods of no power. the NCD2100 has two programming modes to set the value stored in the non-volatile memory, they are: ? all-bits programming mode: program all bits of the non-volatile memory simultaneously (chk=1). ? single-bit programming mode: program a single memory bit to a logic 1 (chk=0). in this mode the memory bits can only be set to logic 1 and only one bit at a time. programming methods and the tuning capacitance components are discussed below. 3.2 cdac1: capacitor segment 1 (10:9) the two bits in the first capacitive digital to analog converter (cdac1) constitute the control bits of the first capacitance tuning segment. this cdac is the first of two coarse capacitive tuning segments. values of c 1 increment in nominal steps of 6.4pf, varying + 25% due to process variations. control data organization cdac1 cdac2 cdac3 chk bit 2 bit 1 bit 3 bit 2 bit 1 bit 5 bit 4 bit 3 bit 2 bit 1 109876543210 (msb) (lsb) c load c 0 c 1 c 2 c 3 +++ = bit 2 bit 1 c 1 value 0 0 0 pf 0 1 6.4 pf 1 0 12.8 pf 1 1 19.2 pf
i ntegrated c ircuits d ivision NCD2100 r02 www.ixysic.com 11 3.3 cdac2: capacitor segment 2 (8:6) the three bits of cdac2 comprise the control bits of the second coarse tuning capacitance segment. these c 2 values increment in nominal steps of 1.4pf, varying + 25% due to process variations. 3.4 cdac3: capacitor segment 3 (5:1) the five bits of cdac3 comprise the control bits of the fine tuning capacitance segment. values of c 3 increment in steps of 0.063pf, varying + 25% due to process variations. bit 3 bit 2 bit 1 c 2 value 000 0 pf 0 0 1 1.4 pf 0 1 0 2.8 pf 0 1 1 4.2 pf 1 0 0 5.6 pf 1 0 1 7.0 pf 1 1 0 8.4 pf 1 1 1 9.8 pf bit 5 bit 4 bit 3 bit 2 bit 1 c 3 value 00000 0 pf 00001 0.063 pf 00010 0.126 pf 00011 0.189 pf 00100 0.252 pf 00101 0.315 pf 00110 0.378 pf 00111 0.441 pf 01000 0.504 pf 01001 0.567 pf 01010 0.630 pf 01011 0.693 pf 01100 0.756 pf 01101 0.819 pf 01110 0.882 pf 01111 0.945 pf 10000 1.008 pf 10001 1.071 pf 10010 1.134 pf 10011 1.197 pf 10100 1.260 pf 10101 1.323 pf 10110 1.386 pf 10111 1.449 pf 11000 1.512 pf 11001 1.575 pf 11010 1.638 pf 11011 1.701 pf 11100 1.764 pf 11101 1.827 pf 11110 1.890 pf 11111 1.953 pf
i ntegrated c ircuits d ivision NCD2100 12 www.ixysic.com r02 3.5 operating modes the NCD2100 functions in one of two different operating modes. the load capacitance pr esented at pin x1 can be controlled by the value loaded into the NCD2100 shift register, or by reading the value stored in the device?s internal non-volatile memory. by default the NCD2100 operates in memory mode so that in most end-user applicat ions the capacitance value corresponds to the calibration information programmed in the memory. whether shift register or memory mode is in use is determined by the logical state at the clk input. ? clk = 1: shift register mode ? clk = 0: memory mode 3.5.1 shift register mode shift register mode provides the means to alter the load capacitance at any time. this mode varies from the memory mode in that the value loaded into the shift register is volatile and will be lost whenever power to the device is removed. because shift register mode is functional over the entire operational range of the NCD2100, the capacitance presented at pin x1 can be modified under all allowable operating conditions. modifying the capacitance is easily accomplished by loading the 11 bit control code into pin da using the clock (clk), with pin pv held low or left open. when pin pv is open circuit, an internal pull down resistor having a nominal value of 180k ? will satisfy the logic 0 requirement. the NCD2100 utilizes a first-in first-out shift register so it is necessary to ensure only 11 rising edges of the clock are applied to the device when entering data. the least significant bit (lsb) of the serial data is the first bit entered into the shi ft register. this bit is chk and does not affect the value of the capacitance. as such, bit chk is a ?don?t care? in shift register mode and may be set to either a logic 0 or a logic 1. when the last bit is entered into the shift register, the clk input must remain at a logic 1 for the control data in the shift register to regulate the capacitor value. should the clock return to zero and then be pulled back up to a logic 1, the value on da when clk transitions to a logic 1 will be loaded into the msb of the shift register causing t he contents in bits 11:1 to shift into locations 10:0. generally resulting in an incorrect control code. 3.5.2 memory mode memory mode is the default mode of operation as this is the most likely in-service condition for a typical application in a finished product. this operational mode uses the value stored in the non-volatile memory to configure the capacitor to the proper value. to facilitate memory mode as the default mode, an internal pull down resistor at the clk pin with a nominal value of 135k ? . provides the required logic 0 state. in addition to the internal pull down resistor at the clk pin there are pull down resistors at the da and pv pins to maintain inert logic 0 states at these inputs ensuring stable and predictable behavior without the need for supplementary external discrete components. the nominal value of the pull down resistor at the da input is 135k ? and the nominal value at pv is 180k ? . to use memory mode, the non-volatile memory within the NCD2100 must be programmed with the appropriate digital code to create the desired capacitive value at the x1 pin.
i ntegrated c ircuits d ivision NCD2100 r02 www.ixysic.com 13 3.6 serial data interface central to the NCD2100 digitally controlled variable capacitor is the serial interface. this simple two-wire interface is used to modify the output capacitance in shift register mode, program the eeprom (programming mode), and verify the memory contents. this interface requires only a clock (clk) and a data line (da) to load control data into the shift register. with this implementation, data is latched in with the rising edge of the clock. in an application with a typical host, data change onto the bus is synchronized with the falling edge of the clock. this way, the time from when data is asserted onto the bus until the data is latched in by the rising edge of the clock is maximized. assuming relatively equal propagation delays for both the clock and data, this co nfiguration will maximize both the setup and hold times as shown in the waveform below. 3.7 programming the non-volatile memory to take advantage of the default operating mode, the non-volatile memory must be programmed with a control code that provides the desired capacitance at pin x1. two programming modes are available to the user. one mode allows for writing the entire contents of the control code into memory with a single programming sequence while the other mode restricts writing the control code to a single bit at a time and only allows changing the control bit value held in memory from a logic 0 to a logic 1. selection of the programming mode is done with the chk control bit. programming mode selection: ? chk = 1: all-bits programming mode ? chk = 0: single-bit programming mode the electrical and timing conditions that must be followed for reliable programming is the same for both programming modes. 3.7.1 memory programming conditions the NCD2100 should be programmed under the following conditions: ? t a = +25c+ 5c ? v dd = +5v+ 0.5v. ? clk: f clk_max = 120khz ? clk: d clk = 50% + 10%. ? pv: programming pulse voltage v pv = +6.5v 0.5v. ? pv: programming pulse width 40ms < t pv < 80ms with a 4 ? s delay from the last rising edge of clk to the rising edge of the pv pulse. ? pv voltage source with minimum current compliance of 4ma. 3.7.2 programming control data into memory the data sequence used to program the memory follows the same structure as used in shift register mode with the lsb being the first bit loaded into the shift register followed by the cdac control bits. although the data sequence for programming the memory is the same as the shift register mode, the data itself is not. when programming the memory, the control data is not entered directly into the shift register. rather, the bit address of a control bit to be programmed with a logic 1 is selected with a logic 0. put another way, invert the control bit values used in shift register mode and enter the inverted value into the shift register when programming the memory. this also applies to the chk bit. for the memory circuits to recognize the all-bits programming mode (chk = 1) a logic 0 must be entered into the shift register least significant bit location. an ex ample of this is shown in section 4.2.1 figure 5 on page 15 . 3.8 verification of memory contents once the eeprom has been programed, the contents can be queried using the two-wire serial bus and properly configuring the pv for data retrieval. to read the memory data output at the pv pin, it must be pulled up to v dd by a 68k ? resistor. v dd and clk must comply with the conditions specified above for programming the memory. memory contents are read one bit at a time by loading the shift register with a logic 1 in all locations except for the bit to be queried who?s location must contain a logic 0. an example is shown in section 4.3 "programming verification? on page 17 . da clk data data data t setup t hold
i ntegrated c ircuits d ivision NCD2100 14 www.ixysic.com r02 4. load capacitance programming procedure determining the proper control code for the desired load capacitance and then programming the control data (trim code) into the non-volatile memory has three phases: ? capacitance trim code determination: the desired capacitance is found by loading different trim codes into the shift register using the shift register mode. ? programming the memory ? verification of the programming figure 4: trim code loading se q uence (shift register mode) 4.1 capacitance trim code determination in this phase, shift register mode is used to find the correct capacitance value. it is determined by sweeping the cdac1, cdac2, and cdac3 values. the shift register value is loaded using pins da and clk as explained in ?serial data interface? on page 13 . shown in figure 4 is an example of loading a trim code into the shift register using shift register mode. the level of the signals is 0v to v dd . in this example (see figure 4 ), the control data trim code = 375 {01011101111} (msb ... lsb) will be entered into the shift register for a nominal output capacitance of 18.649pf. data loaded into the shift register is lsb (chk bit) first. this load capacitance value is synthesized by adding the additional capacitance from cdac1, cdac2 and cdac3 to the base capacitance. in this case, the capacitance value is generated as shown in the following equation: c load =6.6pf+6.4pf+4.2 pf+1.449pf=18.649pf the bits to be loaded for this configuration are: cdac1 ? bit2 = 0 ? bit1 = 1 cdac2 ? bit3 = 0 ? bit2 = 1 ? bit1 = 1 cdac3 ? bit5 = 1 ? bit4 = 0 ? bit3 = 1 ? bit2 = 1 ? bit1 = 1 chk* ? bit1 = 1 * in shift register mode the value of chk is a ?don?t care,? and can therefore be set to logic 1 or logic 0. all 11 bits (see the control data organization table) in ?introduction? on page 10 ) have to be loaded into the shift register. the host program used to load the shift register must ensure this condition is satisfied and that no additional clk pulses be applied. clk da 0 t time chk cdac3 cdac2 cdac1 bit1 bit2 bit3 bit4 bit5 bit1 bit2 bit3 bit1 bit2
i ntegrated c ircuits d ivision NCD2100 r02 www.ixysic.com 15 4.2 programming the memory after the correct trim code is found, it should be programmed into the non-volatile eeprom memory. there are two ways to program the memory, the selection of which is through the value of the chk bit in the programming sequence. in the following examples, the code = 66 (0001000010x) has been determined by means of the shift register mode to provide the optimal capacitance value. each programming mode will be explained in the following sections. 4.2.1 all-bits programming mode (chk=1) in this programming mode, all of the bits are programmed simultaneously. the all-bits programming mode has the advantage of modifying all of the memory bits with a single write and also provides the vehicle for modifying a memory bit from a logic 1 to a logic 0. programming the memory with the binary code 00010000101 using the all-bits programming mode requires loading the shift re gister with the binary code 11101111010. in order to program the memory to code = 66, the sequence shown in figure 5 , has to be followed. in this example, cdac3 bit2, cdac2 bit2, and chk are being programmed to logic 1 while all the other control bits are being programmed to logic 0. selection of which bits in memory are provisioned to logic 1 is by setting a logic 0 in that bit?s address during programming. figure 5: all-bits programming se q uence the programming steps are as follows: 1. determine the desired capacitor value. 2. apply the programming conditions listed in section 3.7.1 "memory programming conditions? on page 13 . 3. send the programming sequence shown in figure 5 . 4. after a 4 ? s delay from the rising edge of clk for cdac1 bit2 the voltage at pv must be set to 6.5v0.5v for a duration of 40ms to 80ms. 5. return clk to a logic 0 concurrent with or after the voltage at pv returns to a logic 0. the contents in memory set the capacitance at x1 whenever clk = 0. 6. verify the memory content, see ?programming verification? on page 17 note: the ?chk? bit is always read as logic 1 in the verification of the programming (see ?programming verification? on page 17 ) 4s 40ms clk da pv time 0 t chk cdac3 cdac2 cdac1 bit1 bit2 bit3 bit4 bit5 bit1 bit2 bit3 bit1 bit2 6.5v 0.5v
i ntegrated c ircuits d ivision NCD2100 16 www.ixysic.com r02 4.2.2 single-bit programming mode (chk=0) in single-bit programming mode, the memory functions as a fuse. this means that once the memory bits have programmed to a logic 1 they can not be cleared using this programming mode. the detailed sequence for single-bit programming of the memory is: 1. determine the desired capacitance value. 2. apply the programming conditions listed in section 3.7.1 "memory programming conditions? on page 13 . 3. erase the memory content if it is not already erased (see ?erasing the memory? on page 17 ). 4. verify the memory content (see ?programming verification? on page 17 ). 5. send the programming sequence to program one bit (see example depicted in figure 6 ). 6. after a 4 ? s delay, the voltage at pv pin must be set to +6.5v0.5v for between 40ms and 80ms. 7. repeat steps 5 & 6 for each additional memory bit that needs be set to a logic 1. 8. verify the memory content (see ?programming verification? on page 17 ). the chk bit is always read as logic 1 during program verification. for this example, cdac2 bit2 needs to be set to a logic 1. depicted in figure 6 cdac2 bit2 is being programmed to a logic 1 in memory by loading a logic 0 into that bit?s address in the shift register while all of the remaining bits in the shift register are set to logic 1. clk loads the entire sequence of these bits into the shift register and when the last bit is loaded clk must remain high. after a minimum wait of 4 ? s, set the pv pin to +6.5v0.5v for between 40ms and 80ms to store a logic 1 into the selected eeprom bit (in this example cdac2 bit2). should one or more memory bits need to be returned to a logic 0 the other programming mode, all-bits mode, can be used to make the changes. figure 6: single-bit programming se q uence clk da pv 4s 40ms 0 t time chk cdac3 cdac2 cdac1 bit1 bit2 bit3 bit4 bit5 bit1 bit2 bit3 bit1 bit2 6.5v 0.5v
i ntegrated c ircuits d ivision NCD2100 r02 www.ixysic.com 17 4.3 programming verification it is possible to verify the contents of the memory one bit at a time. the supply voltage in the verification process must be +5v0.5v. with an external 68k ? pull-up resistor to v dd on the pv pin, a cdac memory bit programmed to a logic 0 will produce a voltage < 0.4*v dd on pv while a memory bit programmed to a logic 1 will produce a voltage > 0.6*v dd . reading the chk bit will only return the logic 1 voltage of 0.6*v dd or greater at the pv pin. the steps that must be followed for verification are: 1. connect a 68k ? resistor from the v dd supply to the pv pin. 2. select the bit to be verified by setting it to logic 0 in the shift register with all the other ten bits set to a logic 1 as shown in figure 7 . hold clk = 1 after the last bit is clocked in for the duration of the measurement. if more than one bit is selected (set to a logic 0), the verification procedure will fail. 3. measure the voltage at the pv pin. repeat steps 2-3 to verify the other bits (cdac3 bit5, cdac3 bit4, etc...) an example of how to verify the value of the cdac2-bit2 bit is provided in figure 7 . figure 7: se q uence for verifying the programmed bits 4.4 erasing the memory restoring the memory to it?s initial factory default code = 0 value is easily accomplished. the memory can be erased using a particular case of the all-bits programming sequence by writing code = 0 with chk = 1 (00000000001). this sequence, depicted in figure 8 , will cause all of the eeprom cdac bits to clear. figure 8: memory erase se q uence clk da pv 0 t time chk cdac3 cdac2 cdac1 bit1 bit2 bit3 bit4 bit5 bit1 bit2 bit3 bit1 bit2 measure voltage at pv pin 0.6 ? v dd 0.4 ? v dd resulting voltage if cdac2-bit2 is set to ?1? resulting voltage if cdac2-bit2 is set to ?0? indeterminate clk da pv 4s 40ms 0 t time chk cdac3 cdac2 cdac1 bit1 bit2 bit3 bit4 bit5 bit1 bit2 bit3 bit1 bit2 6.5v 0.5v
i ntegrated c ircuits d ivision NCD2100 18 www.ixysic.com r02 5. manufacturing information 5.1 moisture sensitivity all plastic encapsulated semiconductor packages are susc eptible to moisture ingression. ixys integrated circuits division clas sified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, ipc/jedec j-std-020 , in force at the time of product evaluation. we test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. failure to adhere to the warnings or limitations as establ ished by the listed specificati ons could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. this product carries a moisture sensitivity level (msl) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard ipc/jedec j-std-033 . 5.2 esd sensitivity this product is esd sensitive , and should be handled according to the industry standard jesd-625 . 5.3 soldering profile this product has a maximum body temperature and time rating as shown below. all other guidelines of j-std-020 must be observed. 5.4 board wash ixys integrated circuits division recommends the use of no-clean flux formulations. however, board washing to remove flux residue is acceptable, and the use of a short drying bake may be necessary. chlorine-based or fluorine-based solvents or fluxes should not be used. clean ing methods that employ ultrasonic energy should not be used. device moisture sensitivity level (msl) rating NCD2100 all versions msl 1 device maximum temperature and duration maximum reflow cycles NCD2100 all versions 260c for 30 seconds 3
i ntegrated c ircuits d ivision NCD2100 r02 www.ixysic.com 19 5.5 mechanical dimensions 5.5.1 NCD2100t tsot-6 package dimensions 5.5.2 NCD2100ttr tsot-6 tape & reel specification dimensions mm (inches) recommended pcb land pattern 2.800.20 (0.1100.00 8) 2.900.15 (0.114 / 0.006) 1.00max (0.039max) 0.95 bsc (0.037 bsc) 1.600.15 (0.0630.006) 0.400.10 (0.0160.004) 0.01min / 0.15max (0.0004min / 0.0059max) 0.870.03 (0.0340.001) gauge pla ne 0.25 bsc (0.010 bsc) +4o / -0o 1 1.05 (0.041) 2.60 (0.102) 0.95 (0.037) 0.60 (0.024) 0.95 bsc (0.037 bsc) 1.90 bsc (0.075 bsc) 0.170.05 (0.00670.0020) 0.450.15 (0.0180.006) dimensions mm (inches) note: de v ices oriented in tape as sho wn. embossment emb ossed carrier top co v er tape thickness 0.102 max. (0.004 max.) 177.8 dia. (7.00 dia.) 3.100.10 (0.1220.004) 1.400.10 (0.0550.004) 1.750.10 (0.0690.004) 8.00 +0.30 -0.10 (0.315 +0.012 -0.004) 2.000.05 (0.0790.002) 4.000.10 (0.1570.004) ? 1.00 +0.25 ( ? 0.039 +0.010) ? 1.550.05 ( ? 0.0610.002) 3.500.05 (0.1380.002) 3.200.10 (0.1260.004) pin 1 4.000.10 (0.1570.004)
i ntegrated c ircuits d ivision NCD2100 20 www.ixysic.com r02 5.5.3 NCD2100m dfn-6 package dimensions 5.5.4 NCD2100mtr dfn-6 tape & reel specification dimensions mm (inches) 2.000.05 (0.0790.002) 0.0250.025 (0.0010.001) 0.250.05 (0.0100.002) pin 1 dot recommended pcb land pattern 2.00 (0.079) 0.30 (0.012) 0.75 (0.030) 1.45 (0.057) 0.85 (0.033) 0.65 (0.026) 2.000.05 (0.0790.002) 0.65 bsc (0.026 bsc) pin 1 id 1.400.05 (0.0550.002) 0.800.05 (0.0310.002) 0.350.05 (0.0140.002) 0.750.05 (0.0300.002) 0.2030.025 (0.0080.001) note: dimensions do not inclu de mold or interlead flash, protr usions or gate bu rrs. dimensions mm (inches) note: de v ices oriented in tape as sho wn. section a-a embossment emb ossed carrier top co v er tape thickness 0.102 max. (0.004 max.) 177.8 dia. (7.00 dia.) 2.300.05 (0.0910.002) 1.000.05 (0.0390.002) 1.750.10 (0.0690.004) 8.00 +0.30 -0.10 (0.315 +0.012 -0.004) 2.000.05 (0.0790.002) 4.000.10 (0.1570.004) 4.00 (0.157) ? 1.00 +0.25 ( ? 0.039 +0.010) ? 1.50 +0.1 -0 ( ? 0.059 +0.004 -0) aa 3.500.05 (0.1380.002) 2.300.05 (0.0910.002) user direction of feed pin 1 specifications: ds-NCD2100-r02 ? copyright 2014, ixys integrated circuits division all rights reserved. printed in usa. 10/17/2014 for additional information please visit www.ixysic.com ixys integrated circuits division makes no representations or warranties with respect to the accuracy or completeness of the co ntents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. neither circuit patent licenses nor indemnity ar e expressed or implied. except as set forth in ixys integrated circuits division?s standard terms and condit ions of sale, ixys integrated circuits division assumes no liability whatsoever, a nd disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringem ent of any intellectual property right. the products described in this document are not designed, intended, authorized or warranted for use as components in systems in tended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of ixys integrated circuits division?s product may resul t in direct physical harm, injury, or death to a person or severe property or environmental damage. ixys integrated circuits divisi on reserves the right to discontinue or make changes to its pr oducts at any time without notice.

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